Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
Train01_Build development environment		Train01_Build development environment
Train02_The basic components of digital circuits		Train02_The basic components of digital circuits
Train03_Synthesizable RTL		Train03_Synthesizable RTL
Train04_Metastable and cross clock domain		Train04_Metastable and cross clock domain
Train05_The basic components of FPGA		Train05_The basic components of FPGA
Train06_Design case of arbitration circuit		Train06_Design case of arbitration circuit
Train07_Tricks of EDA		Train07_Tricks of EDA
Train08_Timing constraint		Train08_Timing constraint
Train09_The basic of High-Level Synthesis		Train09_The basic of High-Level Synthesis
Train10_Embedded development based on ZYNQ		Train10_Embedded development based on ZYNQ
Train11_AXI Protocol		Train11_AXI Protocol
.gitmodules		.gitmodules
README.md		README.md